#Help ltspice mac draw resistor generator

If the source is flagged as a load, the source is forced to be dissipative, that is, the current goes to zero if the voltage between nodes n+ and n- goes to zero or a negative value. This circuit element sources a constant current between nodes n+ and n. Current Source you'll see this first passage: If you look in the manual at LTspice > Circuit Elements > I.

#Help ltspice mac draw resistor generator

I thing that the background of this soft saturation is that LTSpice and also other simulators don't like hard nonlinearities because of convergence problems, but in the case of current generator I haven't found any such parameters which influence the curvature of saturation. It is true as far as the voltage decreases to 1V, but after this, the current begins to degrade. In the simulation, the current of the current generator ramps up linearly, and I would expect that the voltage on the current generator also decreases linearly.

In my opinion, the current should be the prescribed value as far as the voltage across the current generator is above 0V, so the current generator remains as a load.Р В РІР‚СњР В РІР‚С› simulation schematic and a simulation result is also attached. The problem is that I have experienced a soft saturation: as the voltage across the current generator achieves 1V, the current begins to degrade.

In order to model the reality, I would like to use the current generator as 'active load', because in this case it cannot pull the voltage below 0V. The current generator models the output of a specific circuit, so it is a constraint. I would like to use a current generator to pull down the voltage to zero (there is a voltage generator with a series resistor).